Published by Global Banking & Finance Review®
Posted on April 22, 2026
3 min readLast updated: April 23, 2026
Add as preferred source on GoogleTSMC unveiled its A13 (AI‑focused) and N2U (cost‑sensitive) chip technologies, which leverage its existing EUV equipment rather than adopting costly $400 million ASML high‑NA machines. It also previewed advanced multi‑chip stitching by 2028, growing die and memory integration for AI workloads.
By Stephen Nellis and Max A. Cherney
SANTA CLARA, California, April 22 (Reuters) - Taiwan Semiconductor Manufacturing Co on Wednesday showed its newest generation of chip manufacturing technology, saying it expects to be able to create smaller, faster chips without requiring expensive new machines from ASML.
TSMC, the global giant that makes chips for Nvidia, Apple and Google, among many others, showed two improvements of chipmaking technology: One called A13, which will go into production in 2029 and likely be used for artificial intelligence chips, and one called N2U, a more affordable option that can be used to make chips for phones and laptops, as well as AI chips.
For all of the technologies TSMC showed on Wednesday, it is planning to squeeze more gains out of its existing extreme-ultraviolet lithography (EUV) machines from Dutch supplier ASML, rather than move to a newer generation of "high NA" EUV machines, which, at $400 million each, are roughly double the cost of the older machines.
"This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," Kevin Zhang, deputy co-chief operations officer and senior vice president, told Reuters. "This is definitely a strength."
But the gains from smaller and faster chips are modest, and TSMC also showed plans for new technologies in stitching complex AI chips together, which is where analysts expect companies like Nvidia to get the most performance gains in coming years. Where current AI offerings like Nvidia's Vera Rubin, which will come out this year and is made by TSMC, have two large computing chips and eight stacks of high-bandwidth memory, TSMC on Wednesday said that by 2028 it will have the ability to stitch together 10 large chips and 20 memory stacks.
Named after Intel CEO Gordon Moore, his eponymous law predicted that computing power would roughly double every two years while at the same time get cheaper. In recent years, some such as Nvidia's CEO Jensen Huang have said that it no longer holds true.
TSMC is effectively extending Moore's law through the company's technology that stitches multiple chips together, according to Dan Hutcheson, vice chair of TechInsights.
"Moore’s law is morphing from a monolithic, single die in a package to multi-die in a package," he said in an interview. "And that allows the power and performance gains."
But stitching together chips brings challenges of its own. The chips get hot as they operate, and the different materials used to package them together expand at different rates, creating a fresh set of challenges for chip designers.
Large chip packages can bend and crack, which were issues for Nvidia's Rubin AI processor, according to Ian Cutress, chief analyst at consultancy More Than Moore.
"(TSMC) aren't addressing directly how they are solving those challenges," Cutress said.
(Reporting by Stephen Nellis and Max Cherney in Santa Clara, California; Editing by Stephen Coates)
TSMC introduced A13, for high-end AI chips, coming in 2029, and N2U, an affordable chip manufacturing method for phones, laptops, and AI applications.
TSMC is leveraging its existing EUV machines instead of moving to newer 'high NA' EUV machines, which are much more expensive.
The technologies allow for smaller, faster chips, and advances in multi-die packaging for AI chips, enabling more chip and memory stacks to be combined.
Packaging multiple chips increases heat and can cause expansion issues, leading to potential bending and cracking, as seen in Nvidia’s Rubin AI processor.
TSMC extends Moore's law by advancing chip packaging, moving from single die to multi-die packages for better power and performance.
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